INTEL PUBLICATIONS
Timothy J. Maloney

1. N. Khurana, T. Maloney, W. Yeh, "ESD on CHMOS Devices:  Equivalent Circuits, Physical Models and Failure Mechanisms", Proceedings of IRPS, 1985, pp. 212-223.

2.   T. Maloney and N. Khurana, "Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena", EOS/ESD Symposium Proceedings, 1985, pp. 49-54.

3.  T.J. Maloney, "Contact Injection:  A Major Cause of ESD Failure in Integrated Circuits", EOS/ESD Symposium Proceedings, 1986, pp. 166-172.  (Co-winner of Best Paper Award.)

4.   T.J. Maloney, "Designing MOS Inputs and Outputs to Avoid Oxide Failure in the Charged Device Model", EOS/ESD Symposium Proceedings, 1988, pp. 220-227.

5.  H. Pon, G. Kosonocky, T. Maloney, "High Current ESD Damage to MOS I/O Structures Caused by Charged Video Monitor Surfaces and Casings", EOS/ESD Symposium Proceedings, 1989, pp. 78-83.

6.  T.J. Maloney, "Excess Energy Protection Device", US Patent No. 4,821,096 (April 11, 1989).

7.  T.J. Maloney, "Designing MOS Inputs and Outputs to Avoid Oxide Failure in the Charged Device ESD Model", Intel Technology Journal, Winter 1990, pp. 34-41 (an Intel Confidential version of Ref. 4).

8.  W. Baerg, et. al., "The Electrical Resistance Ratio (RR) as a Thin Film Monitor", Proceedings of IRPS, 1990, pp. 119-123.  (Contributed the measurement technique section to this paper, which won the IRPS Best Paper Award.)

9. T.J. Maloney, "Enhanced P+ Substrate Conductance in the Presence of NPN Snapback", 1990 EOS/ESD Symposium Proceedings, pp. 197-205. (Won Best Paper Award.)

10.  B.L. Euzent, T.J. Maloney, and J.C. Donner III, "Reducing Field Failure Rate With Improved EOS/ESD Design", 1991 EOS/ESD Symposium Proceedings, pp. 59-64.

11. B. Bingold, T.J. Maloney, V. Wilson and R. Levi, "Package Effects on Human Body and Charged Device ESD Tests", 1991 EOS/ESD Symposium Proceedings, pp. 144-150.

12. J. Niehof, P.A. Flinn, and T.J. Maloney, "Electromigration Early Resistance Increase Measurements", Proceedings of European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), 1992, pp. 359-362.   Won Best Poster Award.  Also in Quality and Reliability International 9, pp. 295-98 (1993). 

13. T.J. Maloney, "Integrated Circuit Metal in the Charged Device Model:  Bootstrap Heating, Melt Damage and Scaling Laws", 1992 EOS/ESD Symposium Proceedings, pp. 129-134.  Also published in J. Electrostatics, vol. 31 (1993), pp. 313-321.

14. T. J. Maloney, Foreword to Intel Technology Journal Summer 1992 issue, "ESD Protection:  Shelter From the Storms of Electrostatic Discharge". 

15.  R. Aslett, S. Dabral, T. Maloney, "Selecting ESD Protection for Mixed Power Supply Products", 1993 Intel Design Technology Conference, pp. 95-98.

16.  C.C. Johnson, T.J. Maloney and S. Qawami, "Two Unusual HBM ESD Failure Mechanisms on a Mature CMOS Process", 1993 EOS/ESD Symposium Proceedings, pp. 225-231.

17.  S. Dabral, R. Aslett and T. Maloney, "Designing On-Chip Power Supply Coupling Diodes for ESD Protection and Noise Immunity", 1993 EOS/ESD Symposium Proceedings, pp. 239-249.  .  Also in J. Electrostatics, vol. 33 (1994), pp. 357-370.

18.  D. S. Gardner, Q.T. Vu, P.J. van Wijnen, T.J. Maloney and D.B. Fraser, "Embedded Ground Planes Using Sidewall Insulators for High Frequency Interconnections in Integrated Circuits", Proceedings of 1993 International Electron Devices Meeting, paper 10.5.

19.  T.J. Maloney, "Designing and Modeling ESD Diode Strings", Intel Internal Technical Memorandum (ITM) #11763, Rev. 2, March 15, 1994.

20.  T.J. Maloney, "Electrostatic Discharge Protection Circuits Using Biased and Terminated PNP Transistor Chains", US Patent application, filed 3/28/94.  Issued as Patent 5,530,612, June 25, 1996.

21.   Q.T. Vu, P.J. van Wijnen, and T.J. Maloney, "High Speed Sub-Half-Micron Interconnect Characterization up to 18GHz", VLSI Metal Interconnect Conference, Santa Clara, CA, June 1994.

22.  S. Dabral, R. Aslett, T. Maloney, "Core Clamps for Low Voltage Technologies", 1994 EOS/ESD Symposium Proceedings, pp. 141-149.

23.  W. Needham, T.J. Maloney, and Q. Qian, "Using Hall Effect to Monitor Current During IDDQ Testing of CMOS Integrated Circuits", US Patent application, filed 12/29/94.  Issued as Patent 5,570,034, Oct. 29, 1996.

24.  T.J. Maloney and S. Dabral, "Novel Clamp Circuits for IC Power Supply Protection", 1995 EOS/ESD Symposium Proceedings, pp. 1-12.  Revised version published in IEEE Trans. on Components, Packaging, and Manufacturing Technology--Part C, 19, 150-161, July 1996.

25.  N. Clark, K. Parat, T.J. Maloney and Y. Kim, "Melt Filaments in n+pn+ Lateral Bipolar ESD Protection Devices", 1995 EOS/ESD Symposium Proceedings, pp. 295-303.

26.  T.J. Maloney and Q.T. Vu, "T-Matrix De-embedding of IC Metal Transmission Lines to 18 GHz", 46th Automatic RF Techniques Group Conference, Scottsdale, AZ, Nov. 30-Dec. 1, 1995.

27.  K. Parat and T.J. Maloney, "Method and Apparatus for Providing Electrostatic Discharge Protection for High Voltage Inputs", US Patent application, filed 12/21/95.  Issued as Patent 5,825,603, Oct. 20, 1998. 

28.  T.J. Maloney and K. Parat, "A Breakdown-Triggered Transient Discharge Circuit", US Patent application, filed 12/21/95.  Issued as Patent 5,835,328, Nov. 10, 1998.

29.  T.J. Maloney, "Voltage-Tolerant Electrostatic Discharge Protection Device for Integrated Circuit Power Supplies", US Patent application, filed 3/21/96.  Issued as Patent 5,719,737, Feb. 17, 1998.

30.  B. Doyle and T.J. Maloney, "ESD Protection Device Using Static Capacitance Coupling Between Drain and Gate", US Patent application, filed 8/23/96.  Issued as Patent 5,717,560, Feb. 10, 1998.

31.  K. Parat and T.J. Maloney, "Method and Apparatus for Providing Electrostatic Discharge Protection for High Voltage Inputs", US Patent application, filed 10/1/96.  Issued as Patent 5,877,927, March 2, 1999. 

32.  T.J. Maloney and T.M. Eiles, "MOSFET-Based Power Supply Clamps for Electrostatic Discharge Protection of Integrated Circuits", US Patent application, filed 3/25/97.  Issued as Patent 5,907,464, May 25, 1999.

33.  T. Maloney, K. Parat, N.K. Clark, A. Darwish, "Protection of High Voltage Power and Programming Pins", 1997 EOS/ESD Symposium Proceedings, pp. 246-254.  Revised version published in IEEE Trans. on Components, Packaging, and Manufacturing Technology--Part C, 21, 250-256, October 1998.

34.  T. Maloney, “High Voltage Power Supply Clamp Circuitry for Electrostatic Discharge (ESD) Protection”, US Patent application, filed 6/8/98.  Issued as Patent 5,956,219, Sept. 21, 1999.

35.  T. Maloney and W. Kan, “Power Supply Clamp Circuitry for Electrostatic Discharge (ESD) Protection", US Patent application, filed 6/17/98.  Issued as Patent 6,008,970, Dec. 28, 1999.

36.  K. Seshan, T. J. Maloney, and K. Wu, "The Quality and Reliability of Intel's Quarter Micron Process", Intel Technology Journal, Q3 1998, http://developer.intel.com/technology/itj/q31998.htm

37.  T.J. Maloney, "Designing Power Supply Clamps for Electrostatic Discharge Protection of Integrated Circuits", Microelectronics Reliability 38, No. 11, pp. 1691-1703 (November, 1998).

38.  S. Dabral and T.J. Maloney, Basic ESD and I/O Design, published by Wiley Interscience, November 1998, 302 pages.  http://www.amazon.com/exec/obidos/ASIN/0471253596/

39.  T. Maloney, "Through Silicon Modulator and Method Using Polarized Light", US Patent application, filed 12/30/98.  Issued as US Patent 6,269,199, July 31, 2001.

40.  T. Maloney, "Through Silicon Optical Modulator and Method", US Patent application, filed 12/30/98.  Issued as US Patent 6,166,846, Dec. 26, 2000.

41.  T. Maloney, "MOSFET Through Silicon Modulator and Method", US Patent application, filed 12/30/98.  Issued as US Patent 6,323,985, Nov. 27, 2001.

42.  K. K. Parat, N. K. Clark, and T. J. Maloney, "Method for Improved Electrostatic Discharge Protection", US Patent application, filed 7/12/99, then abandoned and re-filed 10/22/01.  Issued as US Patent 6,570,225, May 27, 2003.

43.  T.J. Maloney and W. Kan, "Stacked PMOS Clamps for High Voltage Power Supply Protection", 1999 EOS/ESD Symposium Proceedings, pp. 70-77.  Also published in Microelectronics Reliability 41 No. 3, pp. 335-348 (March, 2001).

44.   S. Voldman, W. Anderson, R. Ashton, M. Chaine, C. Duvvury, T. Maloney and E. Worley, "A Strategy for Characterization and Evaluation of ESD Robustness of CMOS Semiconductor Technologies", 1999 EOS/ESD Symposium Proceedings, pp. 212-224.  Also published in Microelectronics Reliability 41 No. 3, pp. 359-366 (March, 2001).

45.  Y. Ding, M.J. Paniccia, and T.J. Maloney, "Apparatus for Optically Modulating Light Through the Back Side of an Integrated Circuit Die Along the Side Walls of Junctions", US Patent application, filed 11/4/99.  Issued as US Patent 6,480,641, Nov. 12, 2002.

46.  T. Maloney, "Method and Apparatus for Optically Modulating an Optical Beam with Long Interaction Length Optical Modulator", US Patent application, filed 12/2/99.  Issued as US Patent 6,268,953, July 31, 2001.

47. T. Maloney, "Through-Silicon Optical Modulator Device used for Silicon Debugging", Research Disclosure, No. 429, January 2000, pp. 142-143 [disclosed anonymously by Intel].

48. T.J. Maloney and W. Kan, "RC Timer Scheme", US Patent application, filed June 30, 2000.  Issued as US Patent 6,510,033, Jan. 21, 2003.

49.  B. Kleveland, T.J. Maloney, I. Morgan, L. Madden, T.H. Lee, and S.S. Wong, "Distributed ESD Protection for High-Speed Integrated Circuits", IEEE Electron Device Letters, 21, pp. 390-392 (August 2000).

50. T.J. Maloney, "Output Buffer with Charge-Pumped Noise Cancellation", US Patent application, filed 9/28/00.  Issued as US Patent 6,388,503, May 14, 2002.

51.  L. Clark, P. Elamanchili, and T.J. Maloney, "Electrostatic Discharge Protection Device and Method Therefor", US Patent application (low-leakage power supply clamps for XScale), filed Dec. 22, 2000.  Issued as US Patent 6,867,956, March 15, 2005.

52.  B. Crittenden, A. Volk, and T.J. Maloney, "Dynamic Impedance Matched Driver for Improved Slew Rate and Glitch Termination", US Patent application, filed 12/29/00.  Issued as US Patent 6,420,889, July 16, 2002.

53.  J. Ross and T.J. Maloney, "Buried Intersignal Capacitance" (on-board mode compensation), US Patent application, filed 3/30/01.  Issued as US Patent 6,710,255, March 23, 2004.

54.  T.J. Maloney and A. Ilkbahar, "Method and Apparatus for Electro-static Discharge Protection" (p-bias circuits), US Patent application, filed 3/01.  Issued as US Patent 6,545,520, April 8, 2003.

55.  T.J. Maloney, D.-H. Cho, S.S. Poon and B. Lisenker, "Improving the Balanced Coaxial Differential Probe for High-Voltage Pulse Measurements", 2001 EOS/ESD Symposium Proceedings, pp. 398-407.

56.  T.J. Maloney and S.S. Poon, "Apparatus Providing Electrostatic Discharge Protection Having Current Sink Transistors and Method Therefor" (single RC timer), US Patent application, filed October 12, 2001.  Issued as US Patent 6,862,160, March 1, 2005.

57.  T.J. Maloney and S.S. Poon, "Electrostatic Discharge Protection Circuit Having a Ring Oscillator Timer Circuit", US Patent application, filed April 24, 2002.  Issued as US Patent 7,339,770, March 4, 2008.

58.  S.S. Poon and T.J. Maloney, "New Considerations for MOSFET Power Clamps", 2002 EOS/ESD Symposium Proceedings, pp. 1-5.  Also published in Microelectronics Reliability 43, pp. 987-991 (2003).

59.  T.J. Maloney and S.S. Poon, "Low-Capacitance Electrostatic Discharge Protection Diodes",  US Patent Application, filed December 31, 2002.  Issued as US Patent 7,847,317, December 10, 2010.

60.  T.J. Maloney, "Pulse Coupling Apparatus, Systems, and Methods", US Patent Application, filed June 26, 2003, issued as US Patent 7,541,889, June 2, 2009. 

61.  T.J. Maloney, S.S. Poon and L.T. Clark, "Methods for Designing Low-Leakage Power Supply Clamps", 2003 EOS/ESD Symposium, pp. 27-33.  Also published as "Methods for Designing Low-Leakage ESD Power Supply Clamps" in Journal of Electrostatics 62, (2004) pp. 85-97. 

62.  T.J. Maloney, "Radiation Detector for Electrostatic Discharge", US Patent Application, filed April 30, 2004, issued as US Patent 7,126,356, October 24, 2006.

63.  T.J. Maloney and S.S. Poon, "Using Coupled Transmission Lines to Generate Impedance-Matched Pulses Resembling Charged Device Model ESD", 2004 EOS/ESD Symposium, paper 5A.1, Sept. 2004, pp. 308-315.  Also published in IEEE Trans. On Electronics Packaging Manufacturing, vol. 29, no. 3, pp. 172-178 (July 2006).

64.  T.J. Maloney and S.S. Poon, "Total Charge Theorem for Directional Couplers and Z-matched Coupled Lines", IEEE Microwave and Wireless Components Letters, vol 15, pp. 413-415 (June 2005).

65.  T. Maloney, J. Montoya, and E. Olson, "Unifying Factory ESD Measurements and Component ESD Testing", Intel Q&R Technology Symposium, Hillsboro, OR, Nov. 2004.

66.  T. Maloney and S. Poon, "Pulse Transport Apparatus, Systems, and Methods" (stub pulser), US Patent Application, filed March 31, 2005.  Issued as US Patent 7,239,165, July 3, 2007.

67.  J.A. Montoya and T.J. Maloney, "Unifying Factory ESD Measurements and Component ESD Stress Testing", 2005 EOS/ESD Symposium, paper 3A.6, Sept. 2005, pp. 229-237.

68. T.J. Maloney, "Method and Apparatus for Simulating Electrostatic Discharge Events in Manufacturing and Calibrating Monitoring Equipment", US Patent Application, filed December 23, 2005.

69.  T.J. Maloney, "Relay Actuator Circuit and Method", US Patent Application, filed May 1, 2006.  Issued as US Patent 7,817,400, October 19, 2010.

70.  T.J. Maloney and S.S. Poon, "Using Coupled Lines to Produce Highly Efficient Square Pulses for VF-TLP", 2006 EOS/ESD Symposium Proceedings, pp. 310-317.

71.  S.S. Poon and T.J.  Maloney, "Multi-Stack Power Supply Clamp Circuitry for Electrostatic Discharge Protection", US Patent application, filed Sept. 30, 2004.  Issued as US Patent 7,230,806, June 12, 2007.  

72.  T.J. Maloney, "Instrument for Calibrating Antenna-based ESD Detectors", First Annual International ESD Workshop, May, 2007, pp. 274-288.

73.  T.W. Chen, C. Ito, T.J. Maloney, W. Loh, and R.W. Dutton, "Gate Oxide Reliability Characterization in the 100ps Regime with Ultra-fast Transmission Line Pulsing System", 2007 EOS/ESD Symposium Proceedings, pp. 102-106.

74.  S.S. Poon and T.J. Maloney, "Shielded Cable Discharge Induces Current on Interior Signal Lines", 2007 EOS/ESD Symposium Proceedings, pp. 311-317.

75.  T.J. Maloney, A. Martwick, K. Wang, "Measuring Electric and Magnetic Field", US Patent application, filed Aug. 30, 2007.  Issued as US Patent 7,750,629, July 6, 2010.

76.  T.J. Maloney, "CDM Protection, Testing and Factory Monitoring is Easier Than You Think", 2007 Taiwan ESD Conference Proceedings, pp. 2-8 (invited keynote speech and paper).

77.  Year In Review summary, ESD and Latchup.  Invited presentation at IEEE International Reliability Physics Symposium, April 28, 2008.

78.  T.W. Chen, T.J. Maloney, and B. Chou, "Detecting E and H Fields with Microstrip Transmission Lines", 2008 EMC Symposium, August 2008.

79.  B. Chou, T.J. Maloney, and T.W. Chen, "Wafer-Level Charged Device Model Testing", 2008 EOS/ESD Symposium Proceedings, pp. 115-124.

80. T.J. Maloney, "Fast Evaluation of TLP Transients with Elmore Delay Methods", 3rd Annual International ESD Workshop, May, 2009.

81.  T.J. Maloney, "Evaluating TLP Transients and HBM Waveforms", 2009 EOS/ESD Symposium Proceedings, pp. 143-151.

82.  T.J. Maloney and B. Chou, "Control Circuit Having a Delay-Reduced Inverter", US Patent Application filed Dec. 17, 2009.  Issued as US Patent 8,339,756, Dec. 25, 2012.

83.  T.J. Maloney, "Primary and Induced Currents from Cable Discharges", 2010 IEEE EMC Symposium, July 2010, pp. 686-691.

84.  T.J. Maloney, "HBM Tester Waveforms, Equivalent Circuits, and Socket Capacitance", 2010 EOS/ESD Symposium, pp. 407-415. Also published in Microelectronics Reliability, vol. 53, pp. 184-189 (2013).

85.  N. Jack, T.J. Maloney, B. Chou and E. Rosenbaum, "WCDM2--Wafer-Level Charged Device Model Testing with High Repeatability", 2011 Int'l Reliability Physics Symposium, pp. 409-416.

86. T.J. Maloney, "HBM Tester RC Elements Extracted from the Rise Time of the Total Charge", 5th Annual International ESD Workshop, May, 2011.

87.  T.J. Maloney, "Easy Access to Pulsed Hertzian Dipole Fields Through Pole-Zero Treatment", cover article, IEEE EMC Society Newsletter, Summer 2011, pp. 34-42.

88.  T.J. Maloney and A. Daniel, "Filter Models of CDM Measurement Channels and TLP Device Transients", 2011 EOS/ESD Symposium Proceedings, pp. 386-394.

89. E.M. Fledell, P.B. Fischer, R.E. Swart, T.J. Maloney, and J.D. Pippin, "An Interposer to Regulate Current for Wafer Test Tooling", US Patent application, filed March 6, 2012.  Issued as US Patent 9,391,447, July 12, 2016.

90. Hyvonen, C.P. Joshi, and T.J. Maloney, "Electrostatic Discharge Clamp Compatible with a Fast Ramping Supply",  US Patent application, filed March 22, 2012. Issued as US Patent 9,368,956, June 14, 2016.

91. T.J. Maloney, "Simplified Modeling of CDM Testers", ESD Association tutorial, Seattle, WA, June 10, 2012.

92. T.J. Maloney, "Novel Equivalent Circuit for Zin of an Arbitrarily Terminated Transmission Line", August 2012 Technical Tidbit at http://emcesd.com, see http://emcesd.com/tt2012/tt081012.htm.  

93.  T.J. Maloney, "Antenna Response to CDM E-fields", 2012 EOS/ESD Symposium, Sept. 2012, pp.269-278.

94. Lyle D. Nelsen, Steven B. Heymann, Mark E. Hogsett, and Timothy J. Maloney, Provisional Application, "In-tool ESD Events Monitoring Method and Apparatus", filed with US Patent Office (ITW Ref. 60834-US) Dec. 26, 2013. Issued as US Patent 9,671,448, June 6, 2017 (without TJM, as Intel dropped out during pendency).

95. T.J. Maloney, L. Jiang, S.S. Poon, K.B. Kolluru, and AKM Ahsan, "Achieving Electrothermal Stability in Interconnect Metal During ESD Pulses", 2013 International Reliability Physics Symposium Proceedings, Poster EL-1 (Monterey, CA, April 15-18, 2013).

96.  T.J. Maloney, "Pulsed Hertzian Dipole Radiation and Electrostatic Discharge Events in Manufacturing", IEEE EMC Society Magazine, Q3/2013 issue, pp. 49-57.

97.  T.J. Maloney and N. Jack, "CDM Tester Properties as Deduced from Waveforms", 2013 EOS/ESD Symposium, Sept. 2013, pp. 374-382. Expanded version in IEEE Trans. Device and Materials Reliability, vol. 14, no. 3, pp. 792-800, Sept. 2014.

98.  A. Steinman and T.J. Maloney, "Measuring Handler CDM Stress Provides Guidance for Factory Static Controls", 2014 EOS/ESD Symposium, Sept. 2014, pp. 46-52.

99. T.J. Maloney, "Versatile Models and Expanded Application of the IEC 61000-4-2 Test", 2015 EOS/ESD Symposium, paper 7B.3, Sept. 2015.

100. N. Jack and T.J. Maloney, "Low Impedance Contact CDM", 2015 EOS/ESD Symposium, paper 8A.2, Sept. 2015.

101. T.J. Maloney, "Modeling Feedback Effects in Metal Under ESD Stress", 2016 International Reliability Physics Symposium Proceedings, Paper 6A.4  (Pasadena, CA, April 18-21, 2016).

102. T.J. Maloney, "Unified Model of 1-D Pulsed Heating, Combining Wunsch-Bell with the Dwyer Curve", 2016 EOS/ESD Symposium, paper 7A.2, Sept. 2016.

103. T.J. Maloney, "Skin-depth Losses in Measurement Cables and Their Effect on CDM Waveforms," 2017 International ESD Workshop, Lake Tahoe, CA, May 2017.

104. T.J. Maloney, "The Case for Measurement and Analysis of ESD Fields in Semiconductor Manufacturing," 2018 IEEE Electromagnetic Compatibility Symposium, Long Beach, CA, July 2018.

105. T.J. Maloney, "A Turnkey Method for Calculating Coaxial Cable Loss Effects on CDM Waveforms," Poster 6A, 2018 Electrical Overstress/Electrostatic Discharge Symposium, Reno, NV, Sept. 2018.

106. T.J. Maloney and C. Russ, "Tapered RC Networks for Thermal Modeling of ESD", poster A.5, 2019 International ESD Workshop, Monterey, CA, March 31-April 4, 2019.

107. J.-H. Lee, N.M. Iyer, and T.J. Maloney, "Physical Model for ESD Human Body Model to
Transmission Line Pulse", 2019 International Reliability Physics Symposium Proceedings, Paper 5C.5  Monterey, CA, April 2-4, 2019).

108. T.J. Maloney, "The Case for Measurement and Analysis of ESD Fields in Semiconductor Manufacturing--Update", Keynote Speech, 2019 Taiwan ESD and Reliability Conference, Oct. 2019. 

109. P. Ensaf and T.J. Maloney, "An Experimentally Verified Methodology for Calculating Coaxial Cable Loss Effects on CDM Waveforms", 2020 EOS/ESD Symposium, paper 3B.1.